library verilog;
use verilog.vl_types.all;
entity com is
    port(
        overflow        : out    vl_logic;
        cin             : in     vl_logic;
        wt              : in     vl_logic;
        ent             : in     vl_logic;
        clk             : in     vl_logic;
        en              : in     vl_logic;
        Wr              : in     vl_logic;
        Rd              : in     vl_logic;
        rst             : in     vl_logic;
        sin             : in     vl_logic;
        sout            : in     vl_logic;
        datain          : in     vl_logic_vector(3 downto 0);
        M               : in     vl_logic_vector(1 downto 0);
        RA              : in     vl_logic_vector(1 downto 0);
        s               : in     vl_logic_vector(2 downto 0);
        seg             : out    vl_logic_vector(7 downto 0);
        sel             : out    vl_logic_vector(2 downto 0)
    );
end com;
